1. Technical Field of the Invention
The present invention relates to redundant rows of memory cells for dynamic random access memory (DRAM) devices, and particularly to the use of redundant rows of memory cells for DRAM devices having a twisted bit line architecture.
2. Background of the Invention
A conventional DRAM device includes an array of memory cells organized into rows and columns. Each row of memory cells is coupled to an individual word line, and each column of memory cells is coupled to an individual bit line. The array further includes rows of reference cells which cooperate with a selected row of memory cells to place a charge differential on each pair of bit lines during a memory access operation for determining the data values stored in the memory cells.
In particular, a reference cell and a memory cell from an addressed row are connected to a bit line pair during a memory access operation and present a charge differential thereon to be sensed. The memory cell is then refreshed and the DRAM output is driven (during a memory read operation) to a voltage level representing either a high or a low logic level based upon the polarity of the charge differential.
Memory cell arrays typically employ a twisted bit line architecture in which bit lines of the bit line pairs are twisted at one or more locations so as to compensate for signal coupling to adjacent bit lines. FIG. 1 illustrates a typical twisted bit line architecture for a DRAM device. As can be seen, the twist locations corresponding to a bit line pair are substantially evenly distributed therealong.
Although only two rows of reference cells are needed for an untwisted bit line architecture (a first row of reference cells being connected to the true bit lines and a second row of reference cells being connected to the complement bit lines), a greater number of reference cells are required to execute a memory access operation by a DRAM device employing a twisted bit line architecture. In the conventional DRAM cell array of FIG. 1, four rows of reference cells A-D are required.
The decoding of the four rows of reference cells is dependent upon the location of the addressed row of memory cells relative to the twist locations. For instance, an even (odd) row of memory cells in region X requires reference rows A and B (C and D) to be connected to the bit lines. An even (odd) row of memory cells in region Y requires reference rows B and C (A and D) to be connected to the bit lines. As can be seen, the decoding of rows of reference cells is more complicated in DRAM devices having a twisted bit line architecture.
Conventional DRAM devices may typically include one or more redundant rows of memory cells that are adapted to replace a row of memory cells in the memory cell array having a defect. When redundant rows are implemented in a memory cell array having a twisted bit line architecture, the decoding of the reference row must take into account the location of the redundant row that replaces the defective row.
A prior approach to decoding the rows of reference cells is to dispose one or more redundant rows in each region bounded by bit line twists (regions X--X, Y--Y, Z--Z, etc.) and only replace defective rows with a redundant row in the same region. This approach, however, disadvantageously results in an increase in circuitry overhead and a limited use of the redundant rows, hence poorer efficiency.
In light of the foregoing, there is a need for a DRAM device having a twisted bit line architecture which effectively utilizes redundant rows of memory cells in the event of a memory cell row having a defect.